ORCAD – ALLEGRO – SIGRITY | USER GROUP EVENT
- Morning sessions (PCB Design)
- Afternoon session (PCB Analysis)
Come and see the OrCAD PCB 3D environment that gives you the ability to see a realistic 3D representation of your design including complex via structures, stackups and isolated sections of the board, mechanical elements and enclosures for true visualization. The environment support 3D placements, 3D checking to detect clashes , 3D flex folding, 3D printing and a lots more. In addition this session will present a seamless co-design integration to ECAD-MCAD mechanical systems supporting IPC-2581/STEP/IDF/IDX implementing an advance push-pull model to eliminate file handling.
Flex and Rigid-Flex substrate are becoming common in areas like IoT, wearables, mobile smart devices, medical devices, automotive and consumers. Come and see how OrCAD PCB handle multiple cross-section materials within different stackups in one design, an area-dependent rules with real-time inter-layer checks to meet rigid-flex manufacturing guidelines that help you to avoid costly fabrication errors, a new flex focus automatic arc routing and a 3D flex bend editor that gives the designer the necessary tools to manage and visualize these complex designs.
PCB designers face significant challenges in integrating RF circuits on a mixed-signal design. Today’s advanced designs are more complex and need to incorporate all design portions such as digital, RF/microwave, and analog circuits on the same board. This session will present an RF design productivity of up to %50 and more using a robust set of layout functionalities to handle complex RF designs like the creation and editing of via arrays and RF etch elements that are parameterized to enable their use in RF circuit design creation including an existing library of more than 600 such parameterized elements from microstrip to stripline to lumped components. And the Flexible Shape Editor (FSE) module that includes a robust set of editing functionality to provides a powerful and flexible adjustment/resizing functions for copper editing to modify RF irregular shapes that used heavily in power amplifier and filter circuits. Also will discuss the interfaces with RF simulation tools like ADS
Post-design DFM checks are too late. Even if you’re able to find a mistake, you’re going to lose hours, days, even weeks adjusting your design. Explore with us OrCAD full DFM, Design for Fabrication (DFF), Design for Assembly (DFA), and Design for Test (DFT) checks that you need in real-time while you design, so you can complete your design fast and signoff with confidence.
The PSpice® Systems Option provides designers with a system-level simulation solution for their designs supporting C/C++/SystemC, and Verilog A-ADM. Designers utilize PSpice simulation programs for accurate analog and mixed-signal simulations supported by a wide range of board-level models. MATLAB Simulink is a platform for multi-domain simulation and model-based design of dynamic systems. PSpice® Systems Option combines industry-leading simulation tools to provide co-simulations, simulation optimizations, parasitic extraction and re-simulation techniques
We will explore the use of Compliance Kit for PCIe 4, USB3, SFP+, MIPI, HDMI and more.These kits come preloaded with various compliance test bench templates to help sign-off analysis get started very quickly. The major compliance checks are built in the compliance kit, eliminating all the work setting up the simulation test criteria.
DDR4 is common high-speed source-synchronous interface. Explore with us DDR4 post-layout simulations with non-ideal power conditions. Synchronous design performance metrics including eye diagrams with detailed timing measurements and compliance kits vs JEDEC standard are available as outputs.
Ensure you get high performance at a system and component level and at the same time save between 15% and 50% in decoupling capacitor (decap) costs. Cadence Sigrity OptimizePI technology does a complete AC frequency analysis of boards and IC packages. Supporting both pre- and post-layout studies, it quickly pinpoints the best decap selections and placement locations to meet your power-delivery network (PDN) needs at the lowest possible cost.
Ensure reliable power delivery within electrical/thermal co-simulation to maximize accuracy. Cadence Sigrity PowerDC technology provides efficient DC analysis for signoff of IC package and PCB designs. PowerDC technology quickly pinpoints excessive IR drop, along with areas of excess current density and thermal hotspots to minimize your design’s risk of field failure.